Non-volatile memory cell with buried select gate, and method of making same

ABSTRACT

A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate.

TECHNICAL FIELD

The present invention relates to a self-aligned method of forming asemiconductor memory array of floating gate memory cells. The presentinvention also relates to a semiconductor memory array of floating gatememory cells of the foregoing type.

BACKGROUND OF THE INVENTION

Non-volatile semiconductor memory cells using a floating gate to storecharges thereon and memory arrays of such non-volatile memory cellsformed in a semiconductor substrate are well known in the art.Typically, such floating gate memory cells have been of the split gatetype, or stacked gate type.

One of the problems facing the manufacturability of semiconductorfloating gate memory cell arrays has been the alignment of the variouscomponents such as source, drain, control gate, and floating gate. Asthe design rule of integration of semiconductor processing decreases,reducing the smallest lithographic feature, the need for precisealignment becomes more critical. Alignment of various parts alsodetermines the yield of the manufacturing of the semiconductor products.

Self-alignment is well known in the art. Self-alignment refers to theact of processing one or more steps involving one or more materials suchthat the features are automatically aligned with respect to one anotherin that step processing. Accordingly, the present invention uses thetechnique of self-alignment to achieve the manufacturing of asemiconductor memory array of the floating gate memory cell type.

There is a constant need to shrink the size of the memory cell arrays inorder to maximize the number of memory cells on a single wafer, whilenot sacrificing performance (i.e., program, erase and read efficienciesand reliabilities). It is well known that forming memory cells in pairs,with each pair sharing a single source region, and with adjacent pairsof cells sharing a common drain region, reduces the size of the memorycell array. It is also known to form trenches into the substrate, andlocate one or more memory cell elements in the trench to increase thenumber of memory cells that fit into a given unit surface area (see forexample U.S. Pat. Nos. 5,780,341 and 6,891,220). However, such memorycells use the control gate to both control the channel region (in a lowvoltage operation) and to erase the floating gate (in a high voltageoperation). This means the control gate is both a low voltage and highvoltage element, making it difficult to surround it with sufficientinsulation for high voltage operation while not being too electricallyisolated for low voltage operation. Moreover, the proximity of thecontrol gate to the floating needed for an erase operation can result inunwanted levels of capacitive coupling between the control gate and thefloating gate.

U.S. Pat. No. 6,747,310, which is incorporated herein by reference forall purposes, discloses a flash memory cell design that further includesan erase gate and a select gate (and a method of making them same in aself aligned manner). In this design, the channel region running alongthe surface of the substrate is controlled in part by a select gate andin part by the floating gate. The control gate is used to capacitivelycouple to the floating gate for programming, and the erase gate is usedto remove the electrons from the floating gate. However, as thedimensions of the memory cell get smaller and smaller, it becomes moredifficult to efficiently program the memory cell. Specifically, theportion of the channel region under the select gate used to generate hotelectrons becomes too short for efficient hot electron injectionprogramming.

Thus it is an object of the present invention to create a memory cellconfiguration and method of manufacture where the memory cell elementsare self aligned to each other, and where smaller geometries can beachieved without sacrificing (and in fact improving) programmingefficiency.

SUMMARY OF THE INVENTION

The aforementioned problems and needs are addressed by providing for anelectrically programmable and erasable memory device that includes asubstrate of semiconductor material having a first conductivity type anda surface, a trench formed into the surface of the substrate, first andsecond spaced-apart regions formed in the substrate and having a secondconductivity type, with a channel region in the substrate there between,wherein the second region is formed under the trench, and the channelregion includes a first portion that extends substantially along abottom wall of the trench, a second portion that extends substantiallyalong a sidewall of the trench, and a third portion that extendssubstantially along the surface of the substrate, an electricallyconductive floating gate disposed over and insulated from the channelregion third portion for controlling a conductivity of the channelregion third portion, an electrically conductive control gate disposedadjacent to and insulated from the floating gate, an electricallyconductive select gate at least partially disposed in the trench andadjacent to and insulated from the channel region first and secondportions for controlling a conductivity of the channel region first andsecond portions, and an electrically conductive erase gate disposedadjacent to and insulated from the floating gate.

An array of electrically programmable and erasable memory devicesincludes a substrate of semiconductor material having a firstconductivity type and a surface, spaced apart isolation regions formedon the substrate which are substantially parallel to one another andextend in a first direction, with an active region between each pair ofadjacent isolation regions, and each of the active regions including aplurality of pairs of memory cells. Each of the memory cell pairsincludes a pair of trenches formed into the surface of the substrate, apair of second regions each formed in the substrate under one of thepair of trenches, a first region formed in the substrate, wherein a pairof channel regions are each in the substrate between the first regionand one of the second regions, wherein the first and second regions havea second conductivity type, and wherein each of the channel regionsincludes a first portion that extends substantially along a bottom wallof one of the trenches, a second portion that extends substantiallyalong a sidewall of that one trench, and a third portion that extendssubstantially along the substrate surface, a pair of electricallyconductive floating gates each disposed over and insulated from one ofthe channel region third portions for controlling a conductivity of thatchannel region third portion, a pair of an electrically conductivecontrol gates disposed adjacent to and insulated from one of thefloating gates, a pair of electrically conductive select gates each atleast partially disposed in one of the trenches and adjacent to andinsulated from one of the channel region first and second portions forcontrolling a conductivity of those channel region first and secondportions, and an electrically conductive erase gate disposed adjacent toand insulated from the pair of floating gates.

A method of forming a semiconductor memory cell includes forming atrench into a surface of the substrate of semiconductor material havinga first conductivity type, forming first and second spaced-apart regionsin the substrate having a second conductivity type, with a channelregion in the substrate there between, wherein the second region isformed under the trench, and the channel region includes a first portionthat extends substantially along a bottom wall of the trench, a secondportion that extends substantially along a sidewall of the trench, and athird portion that extends substantially along the surface of thesubstrate, forming an electrically conductive floating gate disposedover and insulated from the channel region third portion for controllinga conductivity of the channel region third portion, forming anelectrically conductive control gate disposed adjacent to and insulatedfrom the floating gate, forming an electrically conductive select gateat least partially disposed in the trench and adjacent to and insulatedfrom the channel region first and second portions for controlling aconductivity of the channel region first and second portions, andforming an electrically conductive erase gate disposed adjacent to andinsulated from the floating gate.

A method of forming an array of electrically programmable and erasablememory devices includes forming spaced apart isolation regions on asemiconductor substrate that are substantially parallel to one anotherand extend in a first direction, with an active region between each pairof adjacent isolation regions, wherein the substrate has a surface and afirst conductivity type, and forming a plurality of pairs of memorycells in each of the active regions. The formation of each of the memorycell pairs includes: forming a pair of trenches into the surface of thesubstrate, forming a pair of second regions in the substrate eachdisposed under one of the pair of trenches, forming a first region inthe substrate, wherein a pair of channel regions are each in thesubstrate between the first region and one of the second regions,wherein the first and second regions have a second conductivity type,and wherein each of the channel regions includes a first portion thatextends substantially along a bottom wall of one of the trenches, asecond portion that extends substantially along a sidewall of that onetrench, and a third portion that extends substantially along thesubstrate surface, forming a pair of electrically conductive floatinggates each disposed over and insulated from one of the channel regionthird portions for controlling a conductivity of that channel regionthird portion, forming a pair of an electrically conductive controlgates disposed adjacent to and insulated from one of the floating gates,forming a pair of electrically conductive select gates each at leastpartially disposed in one of the trenches and adjacent to and insulatedfrom one of the channel region first and second portions for controllinga conductivity of those channel region first and second portions, andforming an electrically conductive erase gate disposed adjacent to andinsulated from the pair of floating gates.

Other objects and features of the present invention will become apparentby a review of the specification, claims and appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of a semiconductor substrate used in the firststep of the method of present invention to form isolation regions.

FIG. 1B is a cross sectional view of the structure taken along the line1B-1B showing the initial processing steps of the present invention.

FIG. 1C is a top view of the structure showing the next step in theprocessing of the structure of FIG. 1B, in which isolation regions aredefined.

FIG. 1D is a cross sectional view of the structure in FIG. 1C takenalong the line 1D-1D showing the isolation trenches formed in thestructure.

FIG. 1E is a cross sectional view of the structure in FIG. 1D showingthe formation of isolation blocks of material in the isolation trenches.

FIG. 1F is a cross sectional view of the structure in FIG. 1E showingthe final structure of the isolation regions.

FIGS. 2A-2E are cross sectional views of the semiconductor structure inFIG. 1F taken along the line 2A-2A showing in sequence the steps in theprocessing of the semiconductor structure in the formation of anon-volatile memory array of floating gate memory cells of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The method of the present invention is illustrated in FIGS. 1A to 1F and2A to 2E (which show the processing steps in making the memory cellarray of the present invention). The method begins with a semiconductorsubstrate 10, which is preferably of P type and is well known in theart. The thicknesses of the layers described below will depend upon thedesign rules and the process technology generation. What is describedherein is for the 0.09 urn micron process. However, it will beunderstood by those skilled in the art that the present invention is notlimited to any specific process technology generation, nor to anyspecific value in any of the process parameters described hereinafter.

Isolation Region Formation

FIGS. 1A to 1F illustrate the well known STI method of forming isolationregions on a substrate. Referring to FIG. 1A there is shown a top planview of a semiconductor substrate 10 (or a semiconductor well), which ispreferably of P type and is well known in the art. First and secondlayers of material 12 and 14 are formed (e.g. grown or deposited) on thesubstrate. For example, first layer 12 can be silicon dioxide(hereinafter “oxide”), which is formed on the substrate 10 by any wellknown technique such as oxidation or oxide deposition (e.g. chemicalvapor deposition or CVD) to a thickness of approximately 50-150 Å.Nitrogen doped oxide or other insulation dielectrics can also be used.Second layer 14 can be silicon nitride (hereinafter “nitride”), which isformed over oxide layer 12 preferably by CVD or PECVD to a thickness ofapproximately 1000-5000 Å. FIG. 1B illustrates a cross-section of theresulting structure.

Once the first and second layers 12/14 have been formed, suitable photoresist material 16 is applied on the nitride layer 14 and a masking stepis performed to selectively remove the photo resist material fromcertain regions (stripes 18) that extend in the Y or column direction,as shown in FIG. 1C. Where the photo-resist material 16 is removed, theexposed nitride layer 14 and oxide layer 12 are etched away in stripes18 using standard etching techniques (i.e. anisotropic nitride andoxide/dielectric etch processes) to form trenches 20 in the structure.The distance W between adjacent stripes 18 can be as small as thesmallest lithographic feature of the process used. A silicon etchprocess is then used to extend trenches 20 down into the siliconsubstrate 10 (e.g. to a depth of approximately 500 Å to severalmicrons), as shown in FIG. 1D. Where the photo resist 16 is not removed,the nitride layer 14 and oxide layer 12 are maintained. The resultingstructure illustrated in FIG. 1D now defines active regions 22interlaced with isolation regions 24.

The structure is further processed to remove the remaining photo resist16. Then, an isolation material such as silicon dioxide is formed intrenches 20 by depositing a thick oxide layer, followed by aChemical-Mechanical-Polishing or CMP etch (using nitride layer 14 as anetch stop) to remove the oxide layer except for oxide blocks 26 intrenches 20, as shown in FIG. 1E. The remaining nitride and oxide layers14/12 are then removed using nitride/oxide etch processes, leaving STIoxide blocks 26 extending along isolation regions 24, as shown in FIG.1F.

The STI isolation method described above is the preferred method offorming isolation regions 24. However, the well known LOCOS isolationmethod (e.g. recessed LOCOS, poly buffered LOCOS, etc.) couldalternately be used, where the trenches 20 may not extend into thesubstrate, and isolation material may be formed on the substrate surfacein stripe regions 18. FIGS. 1A to 1F illustrate the memory cell arrayregion of the substrate, in which columns of memory cells will be formedin the active regions 22 which are separated by the isolation regions24. It should be noted that the substrate 10 also includes at least oneperiphery region (not shown) in which control circuitry is formed thatwill be used to operate the memory cells formed in the memory cell arrayregion. Preferably, isolation blocks 26 are also formed in the peripheryregion during the same STI or LOCOS process described above.

Memory Cell Formation

The structure shown in FIG. 1F is further processed as follows. FIGS. 2Ato 2E show the cross sections of the structure in the active regions 22from a view orthogonal to that of FIG. 1F (along line 2A-2A as shown inFIGS. 1C and 1F), as the next steps in the process of the presentinvention are performed concurrently in both regions.

An insulation layer 30 (preferably oxide or nitrogen doped oxide) isfirst formed over the substrate 1 0. The active region portions of thesubstrate 10 can he doped at this time for better independent control ofthe cell array portion of the memory device relative to the peripheryregion. Such doping is often referred to as a V_(t) implant or cell wellimplant, and is well known in the art. During this implant, theperiphery region is protected by a photo resist layer, which isdeposited over the entire structure and removed from just the memorycell array region of the substrate. Next, a layer of polysilicon 32(hereinafter “poly”) is formed with a thickness of approximately1000-2000 over oxide layer 30. At this point, a combination of poly CMPand etch back, with or without a lithography masking step, is performedto limit the width direction of poly layer 32 (i.e. to remove theportions of poly layer 32 in the isolations regions 24). Then, anotherinsulation layer 34 is formed (preferably of oxide, but could instead bea composite of oxide, nitride, oxide sub-layers) over poly layer 32,followed by the formation of another poly layer 36 over oxide layer 34.The resulting structure is shown in FIG. 2A.

A plurality of parallel second trenches 38 are formed in the poly,oxide, poly layers 36, 34, 32 by applying a photo resist (masking)material on the poly layer 36, and then performing a masking step toremove the photo resist material from selected parallel stripe regions.Anisotropic poly and oxide (or combination oxide/nitride/oxide) etchesare used to remove the exposed portions of poly and oxide layers 36 and34 in the stripe regions, leaving second trenches 38 that extend down toand expose poly layer 32. A combination of high temperature oxide (HTO)deposition, nitride deposition, and oxidation is then used to createinsulation layer 40 on the exposed portions of poly layer 36. Poly layer32 is then etched in a self aligned manner with layer 40 to createblocks of the poly layer 32 in the memory cell length direction (whichwill constitute the floating gates). With a masking step, suitable ionimplantation that, depending upon if the substrate is P or N type, mayinclude arsenic, phosphorous, boron and/or antimony (and possibleanneal), is then made across the surface of the structure to form first(source) regions 42 in the substrate portions at the bottom of secondtrenches 36. The source regions 42 are self-aligned to the secondtrenches 38, and have a second conductivity type (e.g. N type) that isdifferent from a first conductivity type of the substrate (e.g. P type).The resulting structure is illustrated in FIG. 2B, where pairs of polyblocks 36/32 are separated by a source region 42.

A masking step is used to fill second trenches 38 with photoresist 44,which also covers a portion of layer 40. An anisotropic oxide etch isthen used to remove exposed portions of oxide layer 30, exposingsubstrate 10. A silicon anisotropic etch process is then used to formthird trenches 46 down into the substrate 10 in each of the activeregions 22 (for example, down to a depth of approximately one featuresize deep, e.g. about 500 Å to several microns with 0.09 um technology).At this point, P-type implantation can be used to adjust the thresholdvoltage of the select (WL) transistor. This can be done in combinationwith the peripheral logic transistor formation. The resulting structureis illustrated in FIG. 2C.

After photoresist 44 is removed, a thermal oxidation process isperformed to form oxide layer 48 on the exposed portions of substrate 10along the sidewalls and bottoms of third trenches 46. This oxidationprocess also thickens oxide layer 30 at the bottom of second trenches38. A thick layer of polysilicon is then formed over the structure,followed by a poly etch back process, which fills second trenches 38with poly blocks 50, and forms poly spacers 52 in third trenches 46.This layer of polysilicon can also be used for gate formation inperipheral region devices. The resulting structure is illustrated inFIG. 2D.

An oxide deposition and anisotropic etch are used to form oxide spacers54 on the outer sides of poly spacers 52. Suitable ion implantation (andanneal) is used to form second (drain) regions 56 in the substrate 10.Insulation material 58, such as BPSG or oxide, is then formed over theentire structure. A masking step is performed to define etching areasover the drain regions 56. The insulation material 58 is selectivelyetched in the masked regions to create contact openings that extend downto drain regions 56. The contact openings are then filled with aconductor metal (e.g. tungsten) to form metal contacts 60 that areelectrically connected to drain regions 56. The final active regionmemory cell structure is illustrated in FIG. 2E.

As shown in FIG. 2E, the process of the present invention forms pairs ofmemory cells that mirror each other, with a memory cell formed on eachside of (and sharing) poly block 50. For each memory cell, first andsecond regions 42/56 form the source and drain regions respectively(although those skilled in the art know that source and drain can beswitched during operation). Poly block 32 constitutes the floating gate,poly block 36 constitutes the control gate, poly spacer 52 constitutesthe select gate, and poly block 50 constitutes the erase gate. Channelregions 62 for each memory cell are defined in the surface portion ofthe substrate that is in-between the source and drain 42/56. Eachchannel region 62 includes three portions: a first (horizontal) portion62 a under third trench 46 (and under select gate 52), a second(vertical) portion 62 b extending along the vertical wall of filledthird trench 46 (and along select gate 52), and a third (horizontal)portion 62 c extending along the surface of the substrate 10 between thesidewall of filled third trench 46 and the source region 42. Each pairof memory cells share a common source region 42 that is disposed underfilled second trench 38 and a common erase gate 50. Similarly, eachdrain region 56 is shared between adjacent memory cells from differentmirror sets of memory cells.

Memory Cell Operation

The operation of the memory cells will now be described. Some aspects ofthe operation and the theory of operation of such memory cells are alsodescribed in U.S. Pat. No. 5,572,054, whose disclosure is incorporatedherein by reference with regard to the operation and theory of operationof a non-volatile memory cell having a floating gate, gate to gatetunneling, and an array of memory cells formed thereby.

To erase a selected memory cell in any given active region 22, a groundpotential is applied to its source 42 and its select and control gates52 and 36. A high-positive voltage (e.g. +10-12 volts) is applied to itserase gate 50. Electrons on the floating gate 32 are induced through theFowler-Nordheim tunneling mechanism to tunnel from the floating gate 32,through the layer 40, and onto the erase gate 50, leaving the floatinggate 32 positively charged. It should be noted that since each erasegate 50 faces a pair of floating gates 32, both floating gates 32 ineach pair will be erased at the same time.

When a selected memory cell is desired to be programmed, a small current(e.g. ˜1 μA) is applied to its drain region 56. A positive voltage levelin the vicinity of the threshold voltage of the MOS structure (on theorder of approximately +0.2 to 1 volt above the drain 56) is applied toits select gate 52, and a voltage of 8-10 V is applied to its controlgate 36. A positive high voltage (e.g. on the order of 5 to 10 volts) isapplied to its source region 42. Because the floating gate 32 is highlycapacitively coupled to the control gate 36, the floating gate 32 “sees”a voltage potential of on the order of +4 to +8 volts. Electronsgenerated by the drain region 56 will flow from that region towards thesource region 42 through the deeply depleted horizontal and verticalportions 62 a/62 b of the channel region 62. As the electrons reach theupper end of the vertical portion 62 b of the channel region 62, wherethey accelerate due to the large potential drop across the gap regionbetween the channel region portions 62 a and 62 c (because the floatinggate 32 is strongly voltage-coupled to the positively charged controlgate 36). The electrons will accelerate and become heated, with most ofthem being injected into and through oxide layer 30 and onto thefloating gate 32, thus negatively charging the floating gate 32. Low orground potential is applied to the source/drain regions 42/56 andcontrol/select gates 36/52 for memory cell rows/columns not containingthe selected memory cell. Thus, only the memory cell in the selected rowand column is programmed.

The injection of electrons onto the floating gate 32 will continue untilthe reduction of the charge on the floating gate 32 can no longersustain a high surface potential in the gap area at the near end ofchannel region 62 c. At that point, the electrons or the negativecharges in the floating gate 32 will decrease the electron flow from thedrain region 56 onto the floating gate 32.

Finally, to read a selected memory cell, ground potential is applied toits source region 42. A read bias voltage (e.g. ˜0.6 to 1 volt) isapplied to its drain region 56, a bias voltage (e.g. 0-3 V) is appliedto its control gate 36, and a bias voltage of approximately 1 to 4 volts(depending upon the power supply voltage of the device) is applied toits select gate 52. If the floating gate 32 is positively charged (i.e.the floating gate is discharged of electrons), then the horizontalchannel region portion 62 c (under the floating gate 32) is turned on.When the select gate 52 is raised to the read potential, the horizontaland vertical channel region portions 62 a/62 b (adjacent the select gate52) are also turned on. Thus, the entire channel region 62 will beturned on, causing electrons to flow from the source region 42 to thedrain region 56. This sensed electrical current would be the “1” state.

On the other hand, if the floating gate 32 is negatively charged, thehorizontal channel region portion 62 c is either weakly turned on or isentirely shut off. Even when the select gate 52 and the drain region 56are raised to their read potentials, little or no current will flowthrough horizontal channel region portion 62 c. In this case, either thecurrent is very small compared to that of the “1” state or there is nocurrent at all. In this manner, the memory cell is sensed to beprogrammed at the “0” state. Ground potential is applied to thesource/drain regions 42/56 and select gates 52 for non-selected columnsand rows so only the selected memory cell is read.

The memory cell array includes peripheral circuitry includingconventional row address decoding circuitry, column address decodingcircuitry, sense amplifier circuitry, output buffer circuitry and inputbuffer circuitry, which are well known in the art.

The present invention provides a memory cell array with superior programefficiencies for any given size memory cell. The program efficiency isenhanced in two ways. First, by forming the select gate in a trench thatextends into the substrate, the length of the channel region portioncontrolled by the selected gate can be increased without increasing thelateral size of the memory cell. The increased length of this portion ofthe channel region allows the electrons to better accelerate beforereaching the floating gate. Second, burying the select gate into thesubstrate results in a vertical portion 62 b of the channel region 62that is directly aimed at the floating gate 32. This means that theaccelerated electrons are traveling directly toward the floating gate32, which results in greater hot electron tunneling compared toelectrons traveling parallel to the insulation layer through which theytunnel. The improved programming efficiency is important for atechnology in which the overall memory cell geometry is constantly beingscaled down in size. While most feature dimensions can and are beingscaled down, the length of channel region portion used for programmingis either reduced at a lesser extent, is preserved, or even is increasedfor better program efficiency. The present invention runs counter to thegeneral trend that reduced memory cell size means all criticaldimensions are reduced in size and length. Finally, having source region42 and drain region 56 separated vertically as well as horizontallyallows for easier optimization of reliability parameters withoutaffecting cell size.

It is to be understood that the present invention is not limited to theembodiment(s) described above and illustrated herein, but encompassesany and all variations falling within the scope of the appended claims.For example, trench 46 can end up having any shape that extends into thesubstrate, with sidewalls that are or are not oriented vertically, notjust the elongated rectangular shape shown in the figures. Although theforegoing method describes the use of appropriately doped polysilicon asthe conductive material used to form the memory cells, it should beclear to those having ordinary skill in the art that in the context ofthis disclosure and the appended claims, “polysilicon” refers to anyappropriate conductive material that can be used to form the elements ofnon-volatile memory cells. 1n addition, any appropriate insulator can beused in place of silicon dioxide or silicon nitride. Moreover, anyappropriate material having etch properties that differ from that ofsilicon dioxide (or any insulator) and from polysilicon (or anyconductor) can be used. Further, as is apparent from the claims, not allmethod steps need be performed in the exact order illustrated orclaimed, but rather in any order that allows the proper formation of thememory cell of the present invention. Additionally, the above describedinvention is shown to be formed in a substrate which is shown to beuniformly doped, but it is well known and contemplated by the presentinvention that memory cell elements can be formed in well regions of thesubstrate, which are regions that are doped to have a differentconductivity type compared to other portions of the substrate. Singlelayers of insulating or conductive material could be formed as multiplelayers of such materials, and vice versa. Lastly, the select gates 52are shown, but need not have, upper portions that extend out of thirdtrenches 46.

References to the present invention herein are not intended to limit thescope of any claim or claim term, but instead merely make reference toone or more features that may be covered by one or more of the claims.Materials, processes and numerical examples described above areexemplary only, and should not be deemed to limit the claims. It shouldbe noted that, as used herein, the terms “over” and “on” bothinclusively include “directly on” (no intermediate materials, elementsor space disposed there between) and “indirectly on” (intermediatematerials, elements or space disposed there between). Likewise, the term“adjacent” includes “directly adjacent” (no intermediate materials,elements or space disposed there between) and “indirectly adjacent”(intermediate materials, elements or space disposed there between). Forexample, forming an element “over a substrate” can include forming theelement directly on the substrate with no intermediatematerials/elements there between, as well as forming the elementindirectly on the substrate with one or more intermediatematerials/elements there between.

1. An electrically programmable and erasable memory device comprising: asubstrate of semiconductor material having a first conductivity type anda surface; a trench formed into the surface of the substrate; first andsecond spaced-apart regions formed in the substrate and having a secondconductivity type, with a channel region in the substrate there between,wherein the second region is formed under the trench, and the channelregion includes a first portion that extends substantially along abottom wall of the trench, a second portion that extends substantiallyalong a sidewall of the trench, and a third portion that extendssubstantially along the surface of the substrate; an electricallyconductive floating gate disposed over and insulated from the channelregion third portion for controlling a conductivity of the channelregion third portion; an electrically conductive control gate disposedadjacent to and insulated from the floating gate; an electricallyconductive select gate at least partially disposed in the trench andadjacent to and insulated from the channel region first and secondportions for controlling a conductivity of the channel region first andsecond portions; and an electrically conductive erase gate disposedadjacent to and insulated from the floating gate.
 2. The device of claim1, wherein the erase gate is disposed over and insulated from the firstregion.
 3. The device of claim 1, wherein the select gate includes anupper portion thereof that extends out of the trench.
 4. The device ofclaim 1, wherein the control gate is disposed over and insulated fromthe floating gate.
 5. The device of claim 1, further comprising: asecond trench formed into the surface of the substrate; a third regionformed in the substrate and having a second conductivity type, with asecond channel region in the substrate between the first and thirdregions, wherein the third region is formed under the second trench, andthe second channel region includes a first portion that extendssubstantially along a bottom wall of the second trench, a second portionthat extends substantially along a sidewall of the second trench, and athird portion that extends substantially along the surface of thesubstrate; an electrically conductive second floating gate disposed overand insulated from the second channel region third portion forcontrolling a conductivity of the second channel region third portion;an electrically conductive second control gate disposed adjacent to andinsulated from the second floating gate; and an electrically conductivesecond select gate at least partially disposed in the second trench andadjacent to and insulated from the second channel region first andsecond portions for controlling a conductivity of the second channelregion first and second portions; wherein the erase gate is disposedadjacent to and insulated from the second floating gate.
 6. An array ofelectrically programmable and erasable memory devices comprising: asubstrate of semiconductor material having a first conductivity type anda surface; spaced apart isolation regions formed on the substrate whichare substantially parallel to one another and extend in a firstdirection, with an active region between each pair of adjacent isolationregions; and each of the active regions including a plurality of pairsof memory cells, wherein each of the memory cell pairs comprises: a pairof trenches formed into the surface of the substrate, a pair of secondregions each formed in the substrate under one of the pair of trenches,a first region formed in the substrate, wherein a pair of channelregions are each in the substrate between the first region and one ofthe second regions, wherein the first and second regions have a secondconductivity type, and wherein each of the channel regions includes afirst portion that extends substantially along a bottom wall of one ofthe trenches, a second portion that extends substantially along asidewall of that one trench, and a third portion that extendssubstantially along the substrate surface, a pair of electricallyconductive floating gates each disposed over and insulated from one ofthe channel region third portions for controlling a conductivity of thatchannel region third portion, a pair of an electrically conductivecontrol gates disposed adjacent to and insulated from one of thefloating gates, a pair of electrically conductive select gates each atleast partially disposed in one of the trenches and adjacent to andinsulated from one of the channel region first and second portions forcontrolling a conductivity of those channel region first and secondportions, and an electrically conductive erase gate disposed adjacent toand insulated from the pair of floating gates.
 7. The array of claim 6,wherein for each of the memory cell pairs, the erase gate is disposedover and insulated from the first region.
 8. The array of claim 6,wherein for each of the memory cell pairs, each of the select gateincludes an upper portion thereof that extends out of one of thetrenches.
 9. The array of claim 6, wherein for each of the memory cellpairs, each of the control gates is disposed over and insulated from oneof the floating gates.
 10. A method of forming a semiconductor memorycell, comprising: forming a trench into a surface of the substrate ofsemiconductor material having a first conductivity type; forming firstand second spaced-apart regions in the substrate having a secondconductivity type, with a channel region in the substrate there between,wherein the second region is formed under the trench, and the channelregion includes a first portion that extends substantially along abottom wall of the trench, a second portion that extends substantiallyalong a sidewall of the trench, and a third portion that extendssubstantially along the surface of the substrate; forming anelectrically conductive floating gate disposed over and insulated fromthe channel region third portion for controlling a conductivity of thechannel region third portion; forming an electrically conductive controlgate disposed adjacent to and insulated from the floating gate; formingan electrically conductive select gate at least partially disposed inthe trench and adjacent to and insulated from the channel region firstand second portions for controlling a conductivity of the channel regionfirst and second portions; and forming an electrically conductive erasegate disposed adjacent to and insulated from the floating gate.
 11. Themethod of claim 10, wherein the erase gate is disposed over andinsulated from the first region.
 12. The method of claim 10, wherein theselect gate includes an upper portion thereof that extends out of thetrench.
 13. The method of claim 10, wherein the control gate is disposedover and insulated from the floating gate.
 14. The method of claim 10,further comprising: forming a second trench into the surface of thesubstrate; forming a third region in the substrate having a secondconductivity type, with a second channel region in the substrate betweenthe first and third regions, wherein the third region is formed underthe second trench, and the second channel region includes a firstportion that extends substantially along a bottom wall of the secondtrench, a second portion that extends substantially along a sidewall ofthe second trench, and a third portion that extends substantially alongthe surface of the substrate; forming an electrically conductive secondfloating gate disposed over and insulated from the second channel regionthird portion for controlling a conductivity of the second channelregion third portion; forming an electrically conductive second controlgate disposed adjacent to and insulated from the second floating gate;and forming an electrically conductive second select gate at leastpartially disposed in the second trench and adjacent to and insulatedfrom the second channel region first and second portions for controllinga conductivity of the second channel region first and second portions;wherein the erase gate is disposed adjacent to and insulated from thesecond floating gate.
 15. A method of forming an array of electricallyprogrammable and erasable memory devices, comprising: forming spacedapart isolation regions on a semiconductor substrate that aresubstantially parallel to one another and extend in a first direction,with an active region between each pair of adjacent isolation regions,wherein the substrate has a surface and a first conductivity type; andforming a plurality of pairs of memory cells in each of the activeregions, wherein the formation of each of the memory cell pairsincludes: forming a pair of trenches into the surface of the substrate,forming a pair of second regions in the substrate each disposed underone of the pair of trenches, forming a first region in the substrate,wherein a pair of channel regions are each in the substrate between thefirst region and one of the second regions, wherein the first and secondregions have a second conductivity type, and wherein each of the channelregions includes a first portion that extends substantially along abottom wall of one of the trenches, a second portion that extendssubstantially along a sidewall of that one trench, and a third portionthat extends substantially along the substrate surface, forming a pairof electrically conductive floating gates each disposed over andinsulated from one of the channel region third portions for controllinga conductivity of that channel region third portion, forming a pair ofan electrically conductive control gates disposed adjacent to andinsulated from one of the floating gates, forming a pair of electricallyconductive select gates each at least partially disposed in one of thetrenches and adjacent to and insulated from one of the channel regionfirst and second portions for controlling a conductivity of thosechannel region first and second portions, and forming an electricallyconductive erase gate disposed adjacent to and insulated from the pairof floating gates.
 16. The method of claim 15, wherein for each of thememory cell pairs, the erase gate is disposed over and insulated fromthe first region.
 17. The method of claim 15, wherein for each of thememory cell pairs, each of the select gates includes an upper portionthereof that extends out of one of the trenches.
 18. The method of claim15, wherein for each of the memory cell pairs, each of the control gatesis disposed over and insulated from one of the floating gates.